The present invention relates to a phase locked loop (PLL) frequency synthesizer, that uses a division value below the decimal point, which realizes a reduction in spurious components.
A PLL frequency synthesizer that uses a division value below the decimal point (xe2x80x9cPLL frequency synthesizerxe2x80x9d) is a frequency synthesizer in which a division value below the decimal point can be set as an average division value by periodically changing the division value of a variable frequency divider. Such a PLL frequency synthesizer has two advantages. That is, (1) a reference frequency (phase comparison frequency) higher than channel interval can be set, and a small division value of a variable frequency divider can be set. Consequently, loop gain of the PLL is high and frequency can be changed at high speed. (2) Since a small division value can be set for a variable frequency divider, phase noise is reduced.
FIG. 13 shows the basic configuration of a conventional PLL frequency synthesizer. This PLL frequency synthesizer includes reference oscillator 1, frequency divider 2 for reference frequency, phase comparator 3, charge pump circuit 4, loop filter 5, voltage-controlled oscillator 6, variable frequency divider 7, division value changing circuit 8, shift register 9, adder 10, accumulator 11, and phase error compensating circuit 12.
Operation of the conventional PLL frequency synthesizer will be described by referring to FIG. 13 and FIG. 14. The reference oscillator 1 outputs a signal Fosc to the frequency divider 2, and the frequency divider 2 outputs a reference frequency signal Fref obtained by frequency-dividing the signal Fosc to the phase comparator 3. The phase comparator 3 compares an output of the variable frequency divider 7 with the reference frequency signal Fref, and outputs an UP signal or a DOWN signal to the charge pump circuit 4. The loop filter 5 receives an output current of the charge pump circuit 4, converts it into voltage, and outputs the voltage to the voltage-controlled oscillator 6. Signal Fvco is output from the voltage-controlled oscillator 6 to the variable frequency divider 7. In such a manner, a PLL loop is configured.
If the PLL uses an integer division value, an integer division value is directly supplied to the variable frequency divider 7. If the PLL uses a division value below the decimal point, the division value changing circuit 8 connected to the shift register 9 is used. By periodically outputting the division value N or N+1 to the variable frequency divider 7, an equivalent division value below the decimal point can be realized. The division value of the variable frequency divider 7 is preset in the shift register 9. The integer division value is supplied to the adder 10 in the division value changing circuit 8, and the division value below the decimal point is supplied to the accumulator 11. Specifically, the division value changing circuit 8 performs a division value changing operation so that N+1 is used only m times in the 2k pulses of the reference frequency signal Fref and N is used (2k m) times, thereby enabling the division value of (N+m)/2k to be equivalently set as an average division value.
FIG. 14 shows an example of the relations among the reference frequency Fref, output of the variable frequency divider 7, and phase error output when m=1 and k=2, that is, the division value is (N+1)/4. In this example, by using the division value N for three outputs out of four outputs of the variable frequency divider 7 and using the division value N+1 for the rest, that is, one output, an average division value of the four division values is set to (N+1)/4. However, phase error occurs between the reference frequency Fref and the output of the variable frequency divider 7, and a phase error amount (phase lead in this case) is output as a signal from the phase comparator 3. Since the cycle of the signals is four times as many as that of the reference frequency Fref signals, a frequency spurious component of xc2xc of the reference frequency occurs.
Consequently, in the conventional technique, as shown in FIG. 13 and FIG. 14, output proportional to output signal of the accumulator 11 is added to the loop filter 5 by the phase error compensating circuit 12, thereby canceling a phase error caused by the frequency dividing operation using the division value below the decimal point.
In a phase error compensation output in the conventional configuration, however, an output pulse has a cycle equal to or higher than integer times of the output signal Fosc of the reference oscillator 1. Even if half of the output signal Fosc is output to the phase error compensating circuit 12, a period of phase error compensation output from the phase error compensating circuit 12 becomes the period (2/Fosc) indicated by the arrows in FIG. 14, so that another spurious component is generated. The spurious component generated at this time has a waveform as shown in FIG. 15. FIG. 15 shows the pulse waveform e(x) which is obtained from Fourier series development based on equation (1) shown in FIG. 16.
When the reference frequency Fref is high and the division value for the reference frequency is small, the value of Fref/Fosc is large, and the pulse width of a phase error compensation output is accordingly wide. When the value is used as a control voltage for the voltage-controlled oscillator 6, due to the pulse waveform, a frequency spurious component is generated.
Specifically, for example, in PHS (Portable Handyphone System), Fvco is equal to 1.7 GHz and Fref is equal to 300 KHz. Thus, the frequencies are relatively high. Although the spurious component generated due to a phase error is attempted to be canceled by the conventional configuration, the width of the phase error compensation pulse cannot be reduced relative to the phase error pulse. Instead, a spurious component due to a phase error compensation pulse is generated.
It is an object of this invention to obtain a PLL frequency synthesizer that uses a division value below the decimal point, which does not generate a spurious component as described above.
According to this invention, there is provided a PLL frequency synthesizer that uses a division value below the decimal point which comprises a phase comparator; a voltage-controlled oscillator; a charge pump circuit; a loop filter; a variable frequency divider capable of periodically changing a division value by a division value changing circuit; and a charge pump bias circuit which supplies modulation reference bias current for canceling a phase error amount to the charge pump circuit.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.